Low Voltage Differential Signalling (LVDS) is a method for high-speed transmission of data over a copper transmission line. In LVDS, the difference in voltage levels between two signal lines forms the transmitted signal. In this way, the effects of noise are substantially reduced. Therefore, LVDS is commonly used for data transmission rates greater than around 100 Mbps over long distances.
FIG. 1 shows an example of a conventional LVDS driver circuit 101. The difference in output signals OUT+ and OUT− on the output terminals 103 and 105 forms the pair of differential signals. The driver circuit 101 includes a DC (direct current) constant current source I1, coupled to voltage supply VDD, four NMOS (n-channel metal oxide semiconductor) switches M1, M2, M3 and M4 and a resistor R1 coupled between the node 107 and voltage supply VSS. The four NMOS switches M1, M2, M3 and M4 are controlled by input voltage signals VIN1 and VIN2 (M1 and M4 receiving input VIN1 and M2 and M3 receiving input VIN2) and direct current through load resistor RL as indicated by the arrows A and B.
In operation, two of the four NMOS switches turn on at a time to steer the current from current source I1 to generate a voltage across RL. To steer current through RL in the direction shown by arrow B, input signal VIN2 goes high, switching on M2 and M3. At this time, input signal VIN1 goes low to keep M1 and M4 off. To steer current through RL in the direction shown by arrow A, input signal VIN1 goes high, switching on M1 and M4. At this time, input signal VIN2 goes low to keep M2 and M3 off.
The circuit shown in FIG. 1 can work well at low frequencies. However, the output switching current is limited by the DC constant current source I1. Since the switching speed of the LVDS driver circuit 101 is proportional to the amount of drive current from current source I1, this means a low switching speed of the LVDS driver circuit 101. This reduces the amplitude of the differential output voltage swing at high frequencies and causes disturbances such as noise, when the driver drives a heavy-load, such as a long cable.
One way to solve this problem is to introduce pre-emphasis into the LVDS driver and this is described in U.S. Pat. No. 6,281,715B1, U.S. Pat. No. 6,288,581B1 and US2004/0124888A1. With pre-emphasis, the differential voltage swing during signal transition is higher than the usual swing for a small proportion of the LVDS clock and becomes stable again for the remainder of the pulse duration. This pre-emphasis pulse compensates for signal degradation (produced by transmission over a long cable for example). For example, the voltage swing may be from 250 mV to around 900 mV for about 1/7 of each LVDS clock cycle and from around 250 mV to around 450 mV for the remainder of each clock cycle.
FIG. 2 shows the driver circuit of U.S. Pat. No. 6,281,715B1. The arrangement includes a current steering circuit 201 (similar to the traditional driver circuit of FIG. 1) together with a pre-emphasis circuit to increase the drive capability of the driver circuit. The pre-emphasis circuit includes transistors M25, M26, M27 and M28, inverters IV2, IV3, IV4 and IV5 and an exclusive-NOR gate XNOR. A truth table for XOR and XNOR is shown below:
TABLE 1Input aInput bXORXNOR000101101010I101
Thus, it would seem that, due to inverters IV2, IV3 and IV4, the signal level at input A of exclusive-NOR gate XNOR would always be opposite to that of input B (which would always provide a zero output). However, the inverters IV2, IV3 and IV4 provide delay matching. Thus, it takes longer for the input signal IN travelling through inverters IV2, IV3 and IV4 to arrive at input B than it does for the input signal IN to arrive at input A. Because of this, inputs A and B of XNOR gate receive signals having the same signal level for a brief time during each switching transition of switches M21 to M24. When this happens, the output of XNOR is high, thereby switching on transistors M25 and M27.
FIG. 3 shows a simplified timing diagram of the signalling in FIG. 2. FIG. 3 shows the signals IN (input signal), IDELAY (output of inverter IV4) and IXNOR (output of XNOR) with respect to time. As can be seen in FIG. 3, between t1 and t2 and between t3 and t4, IN and IDELAY are equal, producing a high output IXNOR. The periods between t1 and t2 and between t3 and t4 correspond to the pre-emphasis pulse.
Thus, in the arrangement of U.S. Pat. No. 6,281,715 B1, illustrated in FIGS. 2 and 3, and also in other known arrangements, an additional current pulse is injected into the driver stage during signal transition and this meets the pre-emphasis requirements. However, the arrangement involves switching the current sources with every transition which causes a lot of switching noise to the neighbouring bias circuitry. This is even more of a problem when a common mode feedback circuit is implemented in the LVDS driver stage.